Legg: Created page with "==Synopsis== All logic gates can be simplified to a NAND Gate. This is a demonstration of a NAND Gate in Verilog ==Notes== I am not an expert, but I discourage using truth..."

2023-09-12T18:51:27Z

Created page with "==Synopsis== All logic gates can be simplified to a NAND Gate. This is a demonstration of a NAND Gate in Verilog ==Notes== I am not an expert, but I discourage using truth..."

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==Synopsis==

All logic gates can be simplified to a NAND Gate. This is a demonstration of a NAND Gate in Verilog

==Notes==
I am not an expert, but I discourage using truth tables in Verilog as doing so may defeat optimizations that the compiler may otherwise perform. This is only included as a reference, not as a best practice.

==Compilation==
<syntaxhighlight lang="bash">
iverilog -o Nand_tb.vvp Nand_tb.v
vvp Nand_tb.vvp
gtkwave Nand_tb.vcd
</syntaxhighlight>
==Code Nand.v by assignment==
<syntaxhighlight lang="Verilog" line='line'>
module Nand(Q,A,B);
output Q;
input A,B;
assign Q = ~(A & B);
endmodule
</syntaxhighlight>
==Code Nand.v by truth table==
<syntaxhighlight lang="Verilog" line='line'>
primitive Nand(Q, A, B);
output Q;
input A,B;
table
0 0 : 1;
0 1 : 1;
1 0 : 1;
1 1 : 0;
x ? : 0;
? x : 0;
endtable
endprimitive
</syntaxhighlight>
==Code Nand_tb.v test bench==
<syntaxhighlight lang="Verilog" line='line'>
`timescale 1ns/1ns
`include "Nand.v"

module Nand_tb;

reg A;
reg B;
wire Q;

Nand uut(Q,A,B);

initial begin
$dumpfile("Nand_tb.vcd");
$dumpvars(0,Nand_tb);

A = 0;
B = 0;
#10;
A = 1;
#10;
B = 1;
#10;
A = 0;
#10;

$display("Test Complete!");
end
endmodule
</syntaxhighlight>
==Pictures==
[[
[[File:GTKWave NAND.png|thumb|GTKWave Signals of a NOR Gate]]
]]

NAND Gate (Verilog) - Revision history

Legg: Created page with "==Synopsis== All logic gates can be simplified to a NAND Gate. This is a demonstration of a NAND Gate in Verilog ==Notes== I am not an expert, but I discourage using truth..."