NOR Gate (Verilog) - Revision history

Legg: /* Code Nor.v by assignment */

2023-09-12T18:46:44Z

Code Nor.v by assignment

Legg: /* Notes */

2023-09-12T18:38:57Z

Notes

Legg at 18:36, 12 September 2023

2023-09-12T18:36:42Z

Legg: Created page with "==Synopsis== All logic gates can be simplified to a NOR Gate. This is a demonstration of a NOR Gate in Verilog ==Notes== ==Compilation== ive..."

2023-09-12T18:10:08Z

Created page with "==Synopsis== All logic gates can be simplified to a NOR Gate. This is a demonstration of a NOR Gate in Verilog ==Notes== ==Compilation== <syntaxhighlight lang="bash"> ive..."

New page

==Synopsis==

All logic gates can be simplified to a NOR Gate. This is a demonstration of a NOR Gate in Verilog

==Notes==

==Compilation==
<syntaxhighlight lang="bash">
iverilog -o Nor_tb.vvp Nor_tb.v
vvp Nor_tb.vvp
gtkwave Nor_tb.vcd
</syntaxhighlight>
==Code Nor.v by assignment==
<syntaxhighlight lang="Verilog" line='line'>
module Nor(Q,A,B);
output Q;
input A,B;
assign Q = ~(A | B);
endmodule
}
</syntaxhighlight>
==Code Nor.v by truth table==
<syntaxhighlight lang="Verilog" line='line'>
primitive Nor(Q, A, B);
output Q;
input A,B;
table
0 0 : 1;
0 1 : 0;
1 0 : 0;
1 1 : 0;
x ? : 0;
? x : 0;
endtable
endprimitive
</syntaxhighlight>
==Code Nor_tb.v test bench==
<syntaxhighlight lang="Verilog" line='line'>
`timescale 1ns/1ns
`include "Nor.v"

module Nor_tb;

reg A;
reg B;
wire Q;

Nor uut(Q,A,B);

initial begin
$dumpfile("Nor_tb.vcd");
$dumpvars(0,Nor_tb);

A = 0;
B = 0;
#10;
A = 1;
#10;
B = 1;
#10;
A = 0;
#10;

$display("Test Complete!");
end
endmodule
</syntaxhighlight>

← Older revision		Revision as of 18:36, 12 September 2023
Line 67:		Line 67:
	endmodule		endmodule
	</syntaxhighlight>		</syntaxhighlight>
		+	==Pictures==
		+	[[File:GTKWave NOR.png\|thumb\|GTKWave Signals of a NOR Gate]]

@@ Line 19: / Line 19: @@
 	assign Q = ~(A | B);
 	endmodule
 </syntaxhighlight>
 ==Code Nor.v by truth table==
 <syntaxhighlight lang="Verilog" line='line'>

@@ Line 4: / Line 4: @@
 ==Notes==
+I am not an expert, but I discourage using truth tables in Verilog as doing so may defeat optimizations that the compiler may otherwise perform.  This is only included as a reference, not as a best practice.
 ==Compilation==